1. Field of the Invention
The present invention relates to a method of scheduling a plurality of tasks for a plurality of memories and memory system thereof, and more particularly, to a method and memory system capable of assigning a priority to the plurality of tasks to execute the plurality of tasks in an optimized order, so as to improve efficiency of the memory system.
2. Description of the Prior Art
A memory controller is commonly utilized for task management in a memory system, especially in a non-volatile memory system. In general, since data stored in a non-volatile memory system may not be lost after electric power of the non-volatile memory system is cut off, the non-volatile memory system becomes an important means to store system data. Among those non-volatile memory systems, NAND flash memory, which has advantages of low power and high speed, becomes popular with the popularization of portable devices in recent years.
However, the NAND flash memory has several drawbacks. For example, each block in the NAND flash memory has an upper limit of access times; besides, data can not be written into a block directly without erasing the block first. In order to overcome these drawbacks, the controller for the NAND flash memory should perform several tasks, such as wear leveling, garbage collection, bad block management, etc. Therefore, the memory controller plays an important role in the NAND flash memory. There are many tasks for the controller of the NAND flash memory to execute. In general, most of the tasks can be classified into four main task types: user data access, metadata management, wear leveling control, and garbage collection. User data access is the access to user data for basic operation, such as read and write. Metadata management is to manage the location for user data access in the memory, e.g. to use a table for mapping which block has data and which block is empty and could be utilized for accessing user data. Wear leveling is to move frequently-modified data to seldom-utilized block and to move seldom-modified data to frequently-utilized block, so as to utilize each block equally to avoid some blocks being damages due to frequent utilization since each block in the NAND flash memory has an upper limit of access times. Garbage collection is to collect usable data in a block before erasing the block.
Please refer to FIG. 1, which is a schematic diagram of a conventional memory system 10. As shown in FIG. 1, the memory system 10 includes a flash memory controller 100 and a flash memory array 150. The flash memory controller 100 communicates with the flash memory array 150 via a flash memory interface. The flash memory controller 100 also communicates with a host device via a host interface, wherein the host device may be a processor or a server required to access data in the memory system 10. The memory controller 100 includes a flash translation layer (FTL) 110 and a physical driver 120. The FTL 110 is utilized for transferring instructions from the host device to the tasks of task types 112A-112D, which can be executed in the flash memory. The FTL 110 further includes an arbitration unit 114, which is utilized for managing and coordinating the tasks. The physical driver 120 is utilized for driving each flash memory in the flash memory array 150 to execute the tasks. All of the flash memories are arranged in the flash memory array 150. The columns in the flash memory array 150 are denoted by channels Ch0-Ch3, and the flash memories in each channel are controlled by enable pins CE0-CE3. Therefore, the channels Ch0-Ch3 and the enable pins CE0-CE3 can be utilized for accessing the memories in the flash memory array 150. Each time the physical driver 120 needs to drive a specific memory, an enable pin corresponding to the specific memory is enabled, and a task can be executed in the specific memory.
According to the above structure, when the host device makes an instruction, the FTL 110 receives the instruction and assigns a task to be executed. The arbitration unit 114 then monitors the physical driver 120. In general, when the physical driver 120 is available, the arbitration unit 114 accesses the physical driver 120 to drive a specific memory in the flash memory array 150 to execute the task. On the other hand, when the physical driver 120 is busy, the task should wait until the former task is complete and then can be executed. Therefore, the performance of the flash memory 10 may be affected and unable to maintain a substantial throughput for a user. Thus, there is a need for improvement of the prior art.